ASIC verification in the next few years - probable trends

There was VHDL, and then came Verilog. Soon SystemC followed. Synopsys lanched Vera and Cadence acquired Verisity. Methodology for designs remained the same but verification tools and techniques have changed by leaps and bounds. Though it is not very blatanly visible since the whole thing is packaged so nicely as a part of the marketing, the fact remains is that we are borrowing technologies that are already standard practices in Software engineering. OOPs is an example. We are just giving it a different flavour. But thats part of the customisation process. Under the hood everything is C or C++.  Barring the performance criteria, we could have used Perl or Python to build simulators. I am not getting into the relative merits vis-a-vis demerits. But there is always a business reason. So the bottom line is we are adapting software engineering methodologies and calling it a layered architecture. My view is if we are borrowing from software then we might as well borrow well. Software engineering is rich terms of methodologies, techniques and development models. I don't see any reason why we cannot bring in Agile or Scrum in our verification development processes. As a forecast I can bet for it that these things will come with a different name and in a more restrictive and proprietary form in future, because it is hardware.

Google has already started developing "go language". Which in future might replace C or C++. It would be an ideal language to develop simulators especially in the case of ASIC Verification, where concurrency plays such an important role. Then there could be a possibility of distributed systems that can probably address the problems of ever increasing design and testbench complexities. Afterall one needs to run the simulation and finish in time. Formal verification has already started influencing verification cycles and productivity. Its not unlikely that an algorithimic approach might take precedence over simulation.

With development in programming logic technology, and better tools for probing signals, people may not even think of simulations in future. The scope is huge. The intensity of renaissance in verification technology can be great. But for the time being what we can do is start adapting software engineering techniques in verification in a proactive way. The wheel is already invented, all we have to do is to use it. And use it well.