Tuesday, December 17, 2013

+: operator in SystemVerilog

An interesting code snippet on usage of +: operator in SystemVerilog.

module test;
bit [7:0] a;
integer i;
integer j;

initial begin
  //a = 8'hAB; 
  //a = 8'h1C; 
  a = 8'h19; 
  i = 4; 
  j = a[i[7:0]];
  $display("a = %h", a); 
  $display("j = %0d", j);
  j = a[0+:3]; 
  j = a[2+:2]; 
  $display("j = %0d", j);
  r = {8{1'b0}};
  $display("r = %h", r);
  #3 $finish;
 end
endmodule

Fibonacci series using SystemVerilog

This is a code for generating Fibonacci series using systemverilog. Recursion is used here in an in-efficient manner. An interesting exercise would be to optimize the following code :-


How to parse command-line arguments in Ruby using OptionParser

I do my scripting in Ruby. I did a lot of scripting in Perl in the past. Usually people prefer getoptlong in Perl to elegantly process command-line arguments.

As with Ruby, there is more than one way to do a particular thing. Ruby has OptionParser.
OptionParser provides a beautiful framework for processing command-line arguments.

Here is a simple demonstration of its usage :-

#!/usr/bin/ruby

require 'optparse'
 
options = {} # Hash where all the options are stored
optparse = OptionParser.new do |opts|
  opts.banner = "Usage: ./script -f "
  opts.on("-f INPUT_FILE", String,"regression list") do |a|
    options[:input_file] = a.chomp
  end
end

if ARGV.empty?  #In case no arguments are provided, help message is displayed
  puts optparse      #./script -h or --help also displays the usage information
  exit
else
  optparse.parse!
end

regression_list = options[:input_file]

< Rest of the code for dealing with the regression list and simulations etc.>

Note - if you use parse! then ARGV is taken as the input argument by default
If you choose to use parse, then you would have to supply the input list explicitly, e.g., ARGV

On the mathematics of verification

Many of you would wonder why I am writing after more than 3 years. My last post was way back in 2010. Well I am still in the business of ASIC verification.  These years had been immensely profound and educating. When you get a glimpse of infinity, all our lifetime's learning appear to be a drop of water in the ocean.

But the quest for knowledge still goes on. I may not be able to ever understand the workings of this universe, but I still want to pursue the quest, even if it is for the mundane.

So in continuation to my last post "on the mathematics of assertions", I have got some really concrete insight into the problem from a much broader perspective. The problem of verification is far more complex than we perceive through dynamic simulations. There is a profound mathematical basis for the behavior of complex boolean systems. I have got a hold on the mathematics, but there is lot of work to be done before I can come to any publishable conclusion.