+: operator in SystemVerilog

An interesting code snippet on usage of +: operator in SystemVerilog.

module test;

bit [7:0] a;
integer i;
integer j;

initial begin

  //a = 8'hAB; 

  //a = 8'h1C; 
  a = 8'h19; 
  i = 4; 

  j = a[i[7:0]];
  $display("a = %h", a); 

  $display("j = %0d", j);
  j = a[0+:3]; 
  j = a[2+:2]; 
  $display("j = %0d", j);

  r = {8{1'b0}};

  $display("r = %h", r);

  #3 $finish;
 end

endmodule